 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| austriamicrosystems ag is now ams ag the technical content of this austriamicrosystems datasheet is still valid. contact information: headquarters: ams ag tobelbaderstrasse 30 8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 e - mail: ams_sales @ams.com please visit our website at www.ams.com
www.austriamicrosystems.com (ptr) revision 1.0.2 1 - 77 datasheet, confidential as3665 9 channel advanced command driven rgb/white led driver 1 general description the as3665 is a capacitive low noise charge pump with 9 current sources. the c harge pump automatically switches between 1:1 and 1:1. 5 modes. the connected current sources have a very low voltage compliance to improve efficiency of the whole system. three current sources have the possibility to operate either from vbat or vcp (especially useful for red leds). the internal control is done by command based pattern generators implemented by three sequencers. these commands are optimized for lighting applications (e.g. ramp up brightness logarithmically). it includes high level commands like conditionals jumps and variables. any of the three sequencers can be dynamically mapped to any of the 9 pwm generators for the leds. the as3665 supports an audio input and sophisticated light patterns can be controlle d by internal digital filters. the as3665 is controlled by i 2 c mode. synchronization over several as3665 is possible by the trig pin. the as3665 is available in a space-saving wl-csp-25 (2.610x2.675mm) 0.5mm pitch and operates over the - 30oc to +85oc temperature range. figure 1. typical operating circuit 2 key features high efficiency capacitive 150ma charge pump with 1:1, 1:1.5 and 1:2 mo des with automatic mode switching; 1:2 mode can be disabled 9 channel high side 20ma current sources - less than 50mv at 10ma dropout voltage - led7,8,9 either powered by vbat or vcp advanced command bas ed pattern generator - 96 x 16 bits program memory - dedicated lighting commands like logarithmic fade - programming control and conditional jumps audio controlled lighting with internal digital filters 3 sequencers - dynamically mapped to 9 pwm generators - internal/external synchronization 9 pwm generators (12 bit resolution) - automatic rgb color correction by t amb i 2 c interface with dedicated en pin available in wl-csp-25 (2.610x2.675mm) 0.5mm pitch 3 applications rgb/white fun or event led for mobile phones or por- table devices; lighting management unit ! " # #$%&' "($'" %%$ $% ) * % +$' ,$' $-% $ ./ 012 2 3 450$2 2 3 450$2 012 " '$ * * *6 *4 * *7 *5 *8 *9 : ; : ; < * =6 = >#< # ?/#.@# <. > *a) * $&% $ 012 > > as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 2 - 77 as3665 datasheet, confidential - pinout 4 pinout pin assignment figure 2. pin assignments wl-csp-25 (2.610x2.675mm) 0.5mm pitch (top view) pin description table 1. pin description for as3665 pin number pin name description a1 c2- charge pump flying capacitor 2 - make a short connection to capacitor c fly2 a2 c1- charge pump flying capacitor 1 - make a short connection to capacitor c fly1 a3 gnd ground supply input pin a4 led9 led9 output - current source from vcp or vbat a5 led8 led8 output - current source from vcp or vbat b1 vbat positive supply input pin b2 c2+ charge pump flying capacitor 2 - make a short connection to capacitor c fly2 b3 addr digital input - i 2 c address select; the va lue of the resistor r addr defines the actual i 2 c address used b4 c 2v5 internal supply - connect a 1f ceramic capacitor between c 2v5 and gnd b5 led7 led7 output - current source from vcp or vbat c1 vcp charge pump output - make a short connection to capacitor c vcpout c2 c1+ charge pump flying capacitor 1 - make a short connection to capacitor c fly1 c3 led3 led3 output - current source from vcp c4 trig digital open drain input/output - used to synchronize across several as3665 c5 gpo digital open drain input/output - general purpose output and adc input d1 led2 led2 output - current source from vcp d2 led1 led1 output - current source from vcp b ! ! " # # $" % &'( " ' $ " ! ! $ b $" # # " ' % &'( as3665 as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 3 - 77 as3665 datasheet, confidential - pinout pin description d3 en digital input - active high enable for as3665 d4 clk32k digital clock input - connect a 32.768khz signal; if this signal is not available, connect this pin to gnd d5 int/audio_in depending on the as3665 configur ation int/audio_in is a 1. open drain digital out put - interrupt output pin 2. analog input - audio or adc signal input e1 led5 led5 output - current source from vcp e2 led4 led4 output - current source from vcp e3 led6 led6 output - current source from vcp e4 scl digital input - clock input for i 2 c communication e5 sda digital open drain input/output - data input/output for i 2 c communication table 1. pin description for as3665 (continued) pin number pin name description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 4 - 77 as3665 datasheet, confidential - absolute maximum ratings pin description 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other cond itions beyond those indicated in table 3, ?electrical characteristics,? on page 5 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments vbat, vcp, c1+, c1-, c2+, c2- to gnd -0.3 +7.0 v vcp to vbat -0.3 v note: diode between vcp and vbat led1, led2...led9 to gnd -0.3 vcp + 0.3 v 7.0 sda, scl, en, clk32k, trig, int/audio_in, gpo, addr, c 2v5 to gnd -0.3 vbat + 0.3 v 7.0 input pin current without causing latchup -100 +100 +i in ma norm: eia/jesd78 continuous power dissipation (t a = +70oc) continuous power dissipation 0.78 mw p t 1 1. depending on actual pcb layout and pcb used continuous power dissipation derating factor 14.2 mw/oc p derate 2 2. p derate derating factor changes the total continuous power dissipation (p t ) if the ambient te mperature is not 70oc. therefore for e.g. t amb =85oc calculate p t at 85oc = p t - p derate * (85oc - 70oc) electrostatic discharge esd hbm 1000 v norm: jedec jesd22-a114f esd cdm 500 v norm: jedec jesd 22-c101c esd mm 200 v norm: jedec jesd 22-a115-a level a temperature ranges and storage conditions junction temperature +150 oc internally limited (overtemperature protection) storage temperature range -55 +125 oc humidity 5 85 % non condensing body temperature during soldering +260 oc according to ipc/jedec j-std-020c ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 5 - 77 as3665 datasheet, confidential - electrical characteristics pin description 6 electrical characteristics v vbat = +2.7v to +5.5v, t amb = -30oc to +85oc, unless otherwise specified. typical values are at v vbat = +3.6v, t amb = +25oc, unless ot herwise specified. table 3. electrical characteristics symbol parameter condition min typ max unit general operating conditions v vbat supply voltage 2.7 3.6 5.5 v v vbatredu ced_func supply voltage as3665 functionally working, but not all parameters fulfilled 2.5 2.7 v i shutdown shutdown current 0.4 1.3 a i stanby standby mode current i 2 c interface active 1.6 6.0 a i active active mode current i 2 c interface active internal oscillator running, program executed 300 a i cp1:1.5 charge pump current charge pump operating in 1:1.5 mode, no load current 0.7 ma t amb operating temperature -30 25 85 oc charge pump v vout charge pump output voltage (pin vout) internally limited 5.5 v i vout charge pump output current 0.0 150 ma efficiency 75 % f clk operating frequency all internal timings are derived from this oscillator if no clock is applied on pin clk32k -10% 2.0 +10% mhz r cp charge pump effective resistance v vbat >=3.3v, i led =100ma 1:1 mode 0.65 1:1.5 mode 3.3 current sources i led1..9 led1...led9 output current range 0.0 25.5 ma i led1..9 led1...led9 current source accuracy i led = 17.5ma -7 +7 % i led1..9 match led1...led9 current source matching i led = 17.5ma 2.5 % i led1..9 leakage led1...led9 leakage current current source off -5 0 +5 a v iled_comp led1...led9 current source voltage compliance minimum voltage between pin vout and led1...led9 or vbat and led7...led9 100 mv adc adc res adc resolution 10 bits adc inl adc integral non- linearity -2 0.2 +2 lsb adc dnl adc differential non- linearity -2 0.25 +2 lsb adc lsb lsb of adc conversion 6.1 mv ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 6 - 77 as3665 datasheet, confidential - electrical characteristics pin description adc toffse t adc temperature measurement offset value 393 oc adc tc code temperature coefficient 1.322 oc/ code t tol temperature sensor accuracy -10 +10 oc audio input r audio_in audio input resistance pin int/audio_in if used as analog input; at maximum input gain (+30db) 20 k digital interface v ih high level input voltage pins sda, scl, en, clk32k, trig, int/audio_in, gpo 1 1.26 v vbat v v il low level input voltage 0.0 0.54 v v ol low level output voltage pins sda, trig, int/audio_in, gpo i ol =3ma 0.2 v i leak leakage current pins sda, scl, en, clk32k, trig, int/ audio_in, gpo 0.01 1.0 a i 2 c mode timings - see figure 3 on page 7 f sclk scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1.3 s t hd:sta hold time (repeated) start condition 2 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su:sta setup time for a repeated start condition 0.6 s t hd:dat data hold time 3 00 . 9 s t su:dat data setup time 4 100 ns t r rise time of both sda and scl signals 20 + 0.1c b 300 ns t f fall time of both sda and scl signals 20 + 0.1c b 300 ns t su:sto setup time for stop condition 0.6 s c b capacitive load for each bus line c b ? total capacitance of one bus line in pf 400 pf c i/o i/o capacitance (sda, scl) 10 pf t timeout i 2 c timeout if scl and sda are low for longer than this time, the as3665 is switched into shutdown mode 5 100 ms table 3. electrical characteristics (continued) symbol parameter condition min typ max unit ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 7 - 77 as3665 datasheet, confidential - electrical characteristics timing diagrams timing diagrams figure 3. i 2 c mode timing diagram 1. the logic input levels v ih and v il allow for 1.8v supplied driving circuit 2. after this period the first clock pulse is generated. 3. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 4. a fast-mode device can be used in a stand ard-mode system, but the requirement t su:dat = to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. 5. this feature can be disabled by setting auto_shutdown (see page 13) =0 scl sda t buf t hd:sta t su:sta repeated start t su:sto t f t su:dat t high t hd:dat t r t low t hd:sta start stop ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 8 - 77 as3665 datasheet, confidential - typical operating characteristics 7 typical operating characteristics v vbat = 3.6v, t a = +25oc (unless otherwise specified). figure 4. efficiency vs. battery voltage, i leds =50ma figure 5. i vbat vs. battery voltage, i leds =50ma 40 45 50 55 60 65 70 75 80 85 90 95 2.6 3 3.4 3.8 4.2 input voltage (v) efficiency pled/pvin (%) white led,2.85v,full bias w hit e led,2 .8 5v , 1/ 4 b ias rgb latbg66,full bias rgb latbg66, 1/4bias full bias = ledx_max=25.5ma 1/4 bias = ledx_max=6.3ma 30 35 40 45 50 55 60 65 70 75 80 85 90 2.6 3 3.4 3.8 4.2 input voltage (v) ibat (ma) white led,2.85v,full bias w hit e led,2 .8 5v , 1/ 4 b ias rgb latbg66,full bias rgb latbg66, 1/4bias full bias = ledx_max=25.5ma 1/4 bias = ledx_max=6.3ma figure 6. i leds vs. battery voltage figure 7. i led1 linearity of current source vs. code full bias = ledx_max=25.5ma 1/4 bias = ledx_max=6.3ma 48 49 50 51 52 2.6 3 3.4 3.8 4.2 input voltage (v) ileds (ma) white led,2.85v,full bias w hit e led,2 .8 5v , 1/ 4 b ias rgb latbg66,full bias rgb latbg66, 1/4bias 0 5 10 15 20 25 0 50 100 150 200 250 digital code iled(ma) ta m b =2 5d eg ta m b =8 5d eg tam b=-25deg figure 8. i led1 monotony of current source vs. co de figure 9. logarithmic pwm ramp -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 50 100 150 200 250 digital code iled-error(ma) tam b=25deg tam b=85deg tam b=-25deg 0 5 10 15 20 25 0 50 100 150 200 250 digital code iled, ibat(ma) iled ibat ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 9 - 77 as3665 datasheet, confidential - typical operating characteristics figure 10. logarithmic pwm ramp figure 11. iled vs. voltage on current source 0.01 0.1 1 10 100 0 50 100 150 200 250 digital code iled, ibat(ma) iled ibat 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1 voltage on current source (v) iled (ma) iled=2 0ma iled=15ma iled=10ma iled=5ma ledx_max=25.5ma figure 12. iled vs. voltage on current source figure 13. iled vs. voltage on current source 0 5 10 15 20 25 30 0 0.2 0.4 0.6 0.8 1 voltage on current source (v) iled (ma) iled=6.3 ma iled=12 .7ma iled=19 .1ma iled=2 5.5ma ledx_max=25.5ma ledx_max=19.1ma ledx_max=12.7ma ledx_max=6.3ma 15 16 17 18 19 20 0 0.2 0.4 0.6 0.8 1 voltage on current source (v) iled (ma) ta m b =2 5d eg ta m b =8 5d eg tamb=-20deg ledx_max=19.1ma ledx_current=19.1ma figure 14. cp in 1:1.5 mode, 150ma load, ac-coupled 500ns/div 20mv/div vcp ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 10 - 77 as3665 datasheet, confidential - detailed description timing diagrams 8 detailed description the as3665 is a fixed frequency charge pump. its output (vout) is connected to nine current sources (led1..led9). a sophisticated command based pattern generator with three sequencers controls the nine pwm generators (12 bit resolution), which are connected to the current sources. commands are downloaded to the as3665 internal memory space and can be executed autonomously in the three sequencers. the commands are optimized for lighting applic ations (e.g. a single command executes logarithmic up dimming). it supports command flow control (like unconditional and conditional jumps). variables which are accessible through the i 2 c interface allow control of the program execution by the i 2 c interface and communication between the three sequencers. the three sequencers can be dynamically assigned to any of the nine outputs (under program control). the as3665 supports an audio input pin int/audio_in whic h allows the control of patterns depending on an audio input signal. this audio input can be feed through internal digital filters for better visual appearance. if the audio feature is not used, the pin int/audio_in can be used as interrupt output 1 to send interrupts. the as3665 is controlled by an i 2 c interface and additional dedicated control lines. an en input operates as a global enable/disable pin and with the pin trig several as3665 can be synchronized in a system. a separate clk32k input can be used to set an exact clock input frequency (all internal timings can be derived either from clk32k or an internal oscillator). the i 2 c address is selectable by the pin addr - see i 2 c address selection on page 40 . a gpo pin can be used for external control or as an additional adc input. the as3665 supports led testing (verific ation of the performance of the con nected leds in an assembled system). following blocks are included inside the as3665: - low noise charge pump opera ting in 1:1, 1:1.5 and 1:2 - automatic mode switching of the charge pump (up & down) - 1mhz oscillator - internal ldo for powering the internal circuitry - audio processing of an analog input signal - overtemperature protection - temperature measurements of the as3665 - 10 bit adc - 9x12 bit, 1x8 bit pwm generators - 6 accurate current s ources connected to vcp - 3 accurate current source configurable to be connected to vbat or vcp (to improve efficiency e.g. of red leds) - internal memory for the program execution - 3 sequencers (3 parallel processing units) - a fully programmable multiplexer connecting the three sequencers to the 10 pwm generators - automatic shutdown to safe power (if scl and sda=0 for 100ms) 1. int/audio_in is an open drain output. severa l interrupt can be easily combined externally. ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 11 - 77 as3665 datasheet, confidential - detailed description internal circuit internal circuit figure 15. as3665 internal circuit ! " ! ! ! ! ! ! " ! ! " " " " " ! !c as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 12 - 77 as3665 datasheet, confidential - detailed description device operating mode device operating mode the operating mode is selected according to the following flowchart: figure 16. as3665 operating mode selection after power on reset, the as3665 waits until en=1 and scl=1 or sda=1 2 and then initializes its internal registers and program memory. once standby mode is reached, the program and setup can be download to the as3665 and by set- ting chip_en =1 the program can be executed. 2. scl and sda is monitored to detect if the i 2 c bus is powered. therefore if en is not used, it can be tied to vbat and the mode selection between shutdown and the other modes is performed by scl and sda. "#$%&'(#$)%*+,-."+). /01,2.% . /345,2."+).367,28.9% . $ :;<0=>:. ?$@a !" #$ % "#&& #'((&) ( *!!((+ ) (%(&) #, - *!!((+ #'((%(&) + # ' % . !"/ #$ $( ' ( +0 (+0 0 (+0 0 ( +0 !" #$ *!!((+ #'((%(&) + ) (%1( + # ' % . !"/ #$ ) / 0 0 "# ) + 0 0 0 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 13 - 77 as3665 datasheet, confidential - detailed description device operating mode if en is pulled low or if the power from the i 2 c bus pullup resistors is removed 3 for more than t timeout , the as3665 enters shutdown 4 . the bit auto_shutdown controls the automatic enteri ng of shutdown mode if the i 2 c bus is disabled: a complete reset cycle can be triggered by setting bit force_reset : 3. therefore scl and sda both are low. table 4. exec_enable register addr: 00h exec_enable register bit bit name default access description 6 chip_en 0h r/w enables the active mode (see figure 16) 0 as3665 standby mode select. set cp_auto_on =0 before setting chip_en =0. output drivers disabled, i 2 c communication possible 1 as3665 active mode select. set cp_auto_on =1 after setting chip_en =1 all functions active, internal oscillator running. 7 ram_init 0h r/w initialization of t he internal memory (see figure 16) 0 memory initialization is finished 1 writing: reset internal program memory and all register from 60h...ffh to their default state reading: memory initialization ongoing; when finished an interrupt can be triggered ( init_ready_int (see page 37) is set) 4. unless auto_shutdown (see page 13) =0 table 5. supervision register addr: 08h supervision register bit bit name default access description 7 auto_shutdown 1h r/w enables the shutdown mode (see figure 16) 0 as3665 cannot enter shutdown do not set pin en=0 if cp_auto_on =1 or cp_on =1 1 as3665 can use shutdown en=0 can be used to enter shutdown mode table 6. reset_control register addr: 3ch reset_control register bit bit name default access description 0 force_reset 0r/w start reset cycle (see figure 16) 0 normal operation 1 reset all registers from 00h...1fh and 5fh to their default value ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 14 - 77 as3665 datasheet, confidential - detailed description clock generation clock generation the as3665 has an internal oscillator running at f clk and an external clock input clk32k: figure 17. clock generation the charge pump and the pwm generator use the f clk clock signal from the internal oscillator. depending on the sig- nal sel_ext_clock , the internal timers and ramp generators use either the pin clk32k as input or f clk divided by 2 and 31: the external clock on clk32k is monitored and if the intern al clock is enabled and no valid clock are detected the reg- ister bit no_extclock_detected (see page 37) is set and an interrupt can be triggered. the internal oscillator is enabled and disabled automatically if register bit osc_always_on is reset: table 7. gpo_control register addr: 04h gpo_control register bit bit name default access description 6 sel_ext_clock 0h r/w enables the external clock on clk32k (see figure 17) 0 use internal f clk clock divided by 31*2 1 use external clock on clk32k (also osc_always_on =0) 1 1. using an external clock has two advantages: a) reduced quiescent current: the internal clock is switched off whenever possible and the timers run from clk32k. b) all timings (e.g. ramp-up, wait) are as accurate as the external clock (usually derived from a crystal). table 8. supervision register addr: 08h supervision register bit bit name default access description 5 osc_always_on 0h r/w enables the internal oscillator (see figure 17) 0 enable internal oscillator only if required 1 the internal oscillator is always running (except in shutdown mode) ! " #$ % &'() " " * + , -#$ # .- as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 15 - 77 as3665 datasheet, confidential - detailed description current sources current sources the internal circuit of the current sources is shown in figure 18 (one current source shown; internally there are 9 iden- tical blocks): figure 18. current sources the processing path consists of the following step (using current source 1 as example): 1. the input of the complete current source block is the register pwm_led1 (see page 22) . this register can be controlled by i 2 c directly or by any of the three sequencers (see section sequencers on page 48 ). 2. the signal is converted from logarithmic domain to linear domain (depending on signal loglin1 (see page 25) ) or multiplied by 16 to obtain 12 bits. 3. it passes an adjustable fader (it can be multiplied by any of the fader registers fader1 , fader2 or fader3 ). if fader_src1 (see page 25) =0, the fader is not used (signal is unchanged). 4. color correction is performed ( temp_int_ext (see page 24) selects either internal temperature measurement or use the register led_temp (see page 24) ). the gain of the color correction can be adjusted by color_slope1 (see page 25) . if color_slope1 =0, color correction is disabled. 5. the resulting 12 bit signal goes to the pmw generator and then to the current source itself. 6. the current source is enabled by led1_on 5 and its current is adjusted by led_current1 and led1_max . 5. led1_on ... led9_on have only effect if all sequencer are switched off ( p1_en (see page 46) =00 and p2_en =00 and p3_en =00). this allow direct control of the leds if no program is executed. !"#$$ %& '() * + , - - ./$0 3 1 2 .2 2 2 2 ! 2 . $$ $ $ 3 & 4 - 5 3& $ 6 + 6 78 9! $%& 7: + & $ 2 ; . <= $9 > + +. & + & ?2 + 22 . & / ddd dddddd ddd ddd ddd < & d $ d $$$ d d $$$ 3 & 2 3& !" as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 16 - 77 as3665 datasheet, confidential - detailed description current sources 7. led7, led8 and led9 have the option to be powered by vbat directly (configured by led7_on_cp ... led9_on_cp ) interface to sequencers pwm_led1 (see page 22) , pwm_led2 ... pwm_led9 is the input pwm value of the current sources (8 bit value). this value can be either controlled by the i 2 c interface or by any of the sequencers (see section sequencers on page 48 ). logarithmic/linear ramping all current sources support logarithmic or linear ramping (selected by register bits loglin1 (see page 25) , loglin2 ... loglin9 ). as light is perceived logarithmically, it is re commended to keep the current sources in logarithmic mode (default setting). rgb color correction the rgb color correction changes the output pwm value depending on the temperature (either the junction tempera- ture if temp_int_ext (see page 24) =0, or a i 2 c value stored in led_temp (see page 24) if temp_int_ext =1). this compen- sates different temperature drifts of leds and keep the white point over temperature. the slope of this temperature compensation is adjustable with the register color_slope1 (see page 25) , color_slope2 ... color_slope9 (set to 0 if the color correction is not used). faders there are three global faders: fader1 (see page 23) , fader2 and fader3 . each current source can be configured to be multiplied by any of the three faders (controlled by fader_src1 (see page 25) , fader_src2 ... fader_src9 ). therefore a fader can operate on any number of curre nt sources in parallel (e.g. to generate smooth fade-out effects on several leds). the faders can operate linear or logarithmic (defined by fader_loglin1 (see page 23) , fader_loglin2 and fader_loglin3 ). analog current setting all current sources can be completely enabled/disable by the register led1_on , led2_on ... led9_on . the actual analog current is set by led_current1 (see page 17) , led_current2 ... led_current9 . the maximum current driving capability of the current sources is set by registers led1_max (see page 20) , led2_max ... led9_max 6 . current source registers analog current setting registers 6. always use the minimum setting for led1_max , led2_max ... led9_max suitable for the application to reduce quiescent current of the internal current source table 9. led_control1 register addr: 02h led_control1 register bit bit name default access description 0 led1_on 0b r/w 0 led1 is off 1 led1 is enabled 1 led2_on 0b r/w 0 led2 is off 1 led2 is enabled 2 led3_on 0b r/w 0 led3 is off 1 led3 is enabled 3 led4_on 0b r/w 0 led4 is off 1 led4 is enabled 4 led5_on 0b r/w 0 led5 is off 1 led5 is enabled ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 17 - 77 as3665 datasheet, confidential - detailed description current sources 5 led6_on 0b r/w 0 led6 is off 1 led6 is enabled 6 led7_on 0b r/w 0 led7 is off 1 led7 is enabled 7 led8_on 0b r/w 0 led8 is off 1 led8 is enabled table 10. led_control2 register addr: 03h led_control2 register bit bit name default access description 0 led9_on 0b r/w 0 led9 is off 1 led9 is enabled table 11. led_current1 register addr: 10h led_current1 register bit bit name default access description 7:0 led_current1 00h r/w sets the current for current source on led1 led1_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 12. led_current2 register addr: 11h led_current2 register bit bit name default access description 7:0 led_current2 00h r/w sets the current for current source on led2 led2_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 9. led_control1 register addr: 02h led_control1 register bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 18 - 77 as3665 datasheet, confidential - detailed description current sources table 13. led_current3 register addr: 12h led_current3 register bit bit name default access description 7:0 led_current3 00h r/w sets the current for current source on led3 led3_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 14. led_current4 register addr: 13h led_current4 register bit bit name default access description 7:0 led_current4 00h r/w sets the current for current source on led4 led4_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 15. led_current5 register addr: 14h led_current5 register bit bit name default access description 7:0 led_current5 00h r/w sets the current for current source on led5 led5_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 19 - 77 as3665 datasheet, confidential - detailed description current sources table 16. led_current6 register addr: 15h led_current6 register bit bit name default access description 7:0 led_current6 00h r/w sets the current for current source on led6 led6_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 17. led_current7 register addr: 16h led_current7 register bit bit name default access description 7:0 led_current7 00h r/w sets the current for current source on led7 led7_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 18. led_current8 register addr: 17h led_current8 register bit bit name default access description 7:0 led_current8 00h r/w sets the current for current source on led8 led8_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 20 - 77 as3665 datasheet, confidential - detailed description current sources table 19. led_current9 register addr: 18h led_current9 register bit bit name default access description 7:0 led_current9 00h r/w sets the current for current source on led9 led9_max 00 01 10 11 0 current source off 1 0.1ma 74.9a 49.8a 24.7a ... 255 25.5ma 19.1ma 12.7ma 6.3ma table 20. led_maxcurr1 register addr: 19h led_maxcurr1 register bit bit name default access description 1:0 led1_max 00b r/w sets the maximum current fo r current source on led1 (see led_current1 on page 17 ) 00 i led1 = 0...25.5ma 01 i led1 = 0...19.1ma 10 i led1 = 0...12.7ma 11 i led1 = 0...6.3ma 3:2 led2_max 00b r/w sets the maximum current fo r current source on led2 (see led_current2 on page 17 ) 00 i led2 = 0...25.5ma 01 i led2 = 0...19.1ma 10 i led2 = 0...12.7ma 11 i led2 = 0...6.3ma 5:4 led3_max 00b r/w sets the maximum current fo r current source on led3 (see led_current3 on page 18 ) 00 i led3 = 0...25.5ma 01 i led3 = 0...19.1ma 10 i led3 = 0...12.7ma 11 i led3 = 0...6.3ma 7:6 led4_max 00b r/w sets the maximum current fo r current source on led4 (see led_current4 on page 18 ) 00 i led4 = 0...25.5ma 01 i led4 = 0...19.1ma 10 i led4 = 0...12.7ma 11 i led4 = 0...6.3ma ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 21 - 77 as3665 datasheet, confidential - detailed description current sources table 21. led_maxcurr2 register addr: 1ah led_maxcurr2 register bit bit name default access description 1:0 led5_max 00b r/w sets the maximum current fo r current source on led5 (see led_current5 on page 18 ) 00 i led5 = 0...25.5ma 01 i led5 = 0...19.1ma 10 i led5 = 0...12.7ma 11 i led5 = 0...6.3ma 3:2 led6_max 00b r/w sets the maximum current fo r current source on led6 (see led_current6 on page 19 ) 00 i led6 = 0...25.5ma 01 i led6 = 0...19.1ma 10 i led6 = 0...12.7ma 11 i led6 = 0...6.3ma 5:4 led7_max 00b r/w sets the maximum current fo r current source on led7 (see led_current7 on page 19 ) 00 i led7 = 0...25.5ma 01 i led7 = 0...19.1ma 10 i led7 = 0...12.7ma 11 i led7 = 0...6.3ma 7:6 led8_max 00b r/w sets the maximum current fo r current source on led8 (see led_current8 on page 19 ) 00 i led8 = 0...25.5ma 01 i led8 = 0...19.1ma 10 i led8 = 0...12.7ma 11 i led8 = 0...6.3ma table 22. led_maxcurr3 register addr: 1bh led_maxcurr3 register bit bit name default access description 1:0 led9_max 00b r/w sets the maximum current fo r current source on led9 (see led_current9 on page 20 ) 00 i led9 = 0...25.5ma 01 i led9 = 0...19.1ma 10 i led9 = 0...12.7ma 11 i led9 = 0...6.3ma ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 22 - 77 as3665 datasheet, confidential - detailed description current sources pwm data input registers table 23. pwm_led1 , pwm_led2 ... pwm_led9 , pwm_gpo registers addr: 80h-89h pwm_led1 , pwm_led2 ... pwm_led9 , pwm_gpo register addr bit name default access description 80h 7:0 pwm_led1 00h r/w pwm value for current source on led1 0l e d 1 o f f ... 255 led1 full scale 81h 7:0 pwm_led2 00h r/w pwm value for current source on led2 0l e d 2 o f f ... 255 led2 full scale 82h 7:0 pwm_led3 00h r/w pwm value for current source on led3 0l e d 3 o f f ... 255 led3 full scale 83h 7:0 pwm_led4 00h r/w pwm value for current source on led4 0l e d 4 o f f ... 255 led4 full scale 84h 7:0 pwm_led5 00h r/w pwm value for current source on led5 0l e d 5 o f f ... 255 led5 full scale 85h 7:0 pwm_led6 00h r/w pwm value for current source on led6 0l e d 6 o f f ... 255 led6 full scale 86h 7:0 pwm_led7 00h r/w pwm value for current source on led7 0l e d 7 o f f ... 255 led7 full scale 87h 7:0 pwm_led8 00h r/w pwm value for current source on led8 0l e d 8 o f f ... 255 led8 full scale 88h 7:0 pwm_led9 00h r/w pwm value for current source on led9 0l e d 9 o f f ... 255 led9 full scale ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 23 - 77 as3665 datasheet, confidential - detailed description current sources rgb color correction, fader and logarithmic/linear registers 89h 7:0 pwm_gpo 00h r/w pwm value for gpo pwm generator (8 bits) 0 pwm gpo off ... 255 pwm gpo full scale table 24. led_control2 register addr: 03h led_control2 register bit bit name default access description 3 temp_comp_mode 1 1. its safe to keep temp_comp_mode at default ?0? 0r/w temperature compensation operating mode 0 normal mode 1 positive values of correction: normal operation negative values of correction: correction value divided by 2 4 fader_loglin1 0r/w fader 1 linear / logarithmic control 0 linear operation 1 logarithmic operation 5 fader_loglin2 0r/w fader 2 linear / logarithmic control 0 linear operation 1 logarithmic operation 6 fader_loglin3 0r/w fader 3 linear / logarithmic control 0 linear operation 1 logarithmic operation table 25. fader1 , fader2 and fader3 registers addr: 9b-9dh fader1 , fader2 and fader3 register addr bit name default access description 9bh 7:0 fader1 00h r/w global fader1 value 0o f f ... 255 full scale 9ch 7:0 fader2 00h r/w global fader2 value 0o f f ... 255 full scale table 23. pwm_led1 , pwm_led2 ... pwm_led9 , pwm_gpo registers (continued) addr: 80h-89h pwm_led1 , pwm_led2 ... pwm_led9 , pwm_gpo register addr bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 24 - 77 as3665 datasheet, confidential - detailed description current sources 9dh 7:0 fader3 00h r/w global fader3 value 0o f f ... 255 full scale table 26. temp_sense_ control register addr: 0eh temp_sense_ control register bit bit name default access description 0 temp_int_ext 0b r/w the rgb color correction uses internal/external source for temperature compensation (see rgb color correction on page 16 ) 0 i 2 c register led_temp is used 1 internal junction temperature measured 1 1 temp_sens_on 0b r/w internal temperature sensor enable 0 internal temperature sensor off 1 internal temperature sensor on 2 temp_meas_busy 0b r internal temperature sensor busy status signal 0 internal temperature sensor off or not busy 1 internal temperature sensor busy 1. set temp_sens_on =1 table 27. led_temp register addr: 1fh led_temp register bit bit name default access description 7:0 led_temp 00h r/w value used for rgb color correction if temp_int_ext =1 (see rgb color correction on page 16 ) 185 -30oc 142 25oc 96 +85oc table 25. fader1 , fader2 and fader3 registers (continued) addr: 9b-9dh fader1 , fader2 and fader3 register addr bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 25 - 77 as3665 datasheet, confidential - detailed description current sources table 28. driver_setup1 register addr: a0h driver_setup1 register bit bit name default access description 4:0 color_slope1 00h r/w led1 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin1 1b r/w led1 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src1 00b r/w led1 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 table 29. driver_setup2 register addr: a1h driver_setup2 register bit bit name default access description 4:0 color_slope2 00h r/w led2 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin2 1b r/w led2 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src2 00b r/w led2 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 26 - 77 as3665 datasheet, confidential - detailed description current sources table 30. driver_setup3 register addr: a2h driver_setup3 register bit bit name default access description 4:0 color_slope3 00h r/w led3 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin3 1b r/w led3 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src3 00b r/w led3 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 table 31. driver_setup4 register addr: a3h driver_setup4 register bit bit name default access description 4:0 color_slope4 00h r/w led4 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin4 1b r/w led4 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src4 00b r/w led4 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 27 - 77 as3665 datasheet, confidential - detailed description current sources table 32. driver_setup5 register addr: a4h driver_setup5 register bit bit name default access description 4:0 color_slope5 00h r/w led5 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin5 1b r/w led5 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src5 00b r/w led5 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 table 33. driver_setup6 register addr: a5h driver_setup6 register bit bit name default access description 4:0 color_slope6 00h r/w led6 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin6 1b r/w led6 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src6 00b r/w led6 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 28 - 77 as3665 datasheet, confidential - detailed description current sources table 34. driver_setup7 register addr: a6h driver_setup7 register bit bit name default access description 4:0 color_slope7 00h r/w led7 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin7 1b r/w led7 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src7 00b r/w led7 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 table 35. driver_setup8 register addr: a7h driver_setup8 register bit bit name default access description 4:0 color_slope8 00h r/w led8 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin8 1b r/w led8 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src8 00b r/w led8 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 29 - 77 as3665 datasheet, confidential - detailed description charge pump charge pump the charge pump used the two flying capacitors c fly1 and c fly2 to operate in 1:1, 1:1. 5 and 1:2 mode boosting the input supply vbat to vout (shown in figure 19 ). an implemented soft start mech anism reduces the inrush current. battery current is smoothed when switching the charge pump on and also at each switching condition. this precaution reduces electromagnetic radiation significantly. figure 19. charge pump table 36. driver_setup9 register addr: a8h driver_setup9 register bit bit name default access description 4:0 color_slope9 00h r/w led9 rgb color correction (see page 16) slope 00h rgb color correction disabled 01h +0.15%/oc ... ... 0fh +2.263%/oc 11h -2.263%/oc ... ... 1fh -0.15%/oc 5 loglin9 1b r/w led9 logarithmic/linear ramping (see page 16) 0 linear ramping/dimming 1 logarithmic ramping/dimming 7:6 fader_src9 00b r/w led9 faders (see page 16) 00 fader disabled 01 use fader1 (see page 23) 10 use fader2 11 use fader3 ! " ! " # $% &'( ) $% $%* +' +' ) # (, -, # as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 30 - 77 as3665 datasheet, confidential - detailed description charge pump the operating modes are controlled according to the following tables: table 37. cp_control register addr: 05h cp_control register bit bit name default access description 1:0 cp_mode 00b r/w operating mode of charge pu mp (in manual mode sets the operating mode, in automatic mode reports the mode) 00 1:1 mode 01 1:1.5 mode 10 1:2 mode 11 reserved - don?t use 3:2 cp_mode_switching 00b r/w mode switching control 00 1:1, 1:1.5 automatically up and down switching 01 1:1, 1:1.5 automatic ally up switching 10 1:1, 1:1.5, 1:2 automatically up switching 11 manual mode switching; mode defined by cp_mode 4 cp_auto_on 1b r/w automatically switch on the charge pump if required 0 charge pump should be enabled by cp_on 1 cp is automatically enabled if a current source is enabled 1 1. exception: led7...led9 if connect ed to vbat. defined by register led7_on_cp , led8_on_cp and led9_on_cp . 5 cp_on 0b r/w automatically switch on the charge pump if required 0 the charge pump stays in 1:1 mode (unless cp_auto_on is set) 1 enable manual or aut omatic mode switching 7:6 cp_down_hyst 00b r/w control the hysteresis for down switching from 1:1.5 to 1:1 mode 00 default hysteresis 01 default-75mv hysteresis 10 default-150mv hysteresis 11 default-225mv hysteresis ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 31 - 77 as3665 datasheet, confidential - detailed description charge pump the charge pump starts operation always in 1:1 mode and re turns back to 1:1 mode if all current sources are switched off 7 . if the voltage across a enabled current source is no long er sufficient to operate th e current source, the charge pump automatically select the next operating m ode (which modes are allowed is controlled by cp_mode_switching . cp_auto_on or cp_on should be set for enabling this logic). in 1:1.5 mode and if cp_mode_switching =00, the charge pump also can automatically sw itch back into 1:1 mode if the voltage across all current sources is sufficiently high to use the more efficient 1:1 mode (a fine adju stment of this hysteresis is possible with cp_down_hyst ). application hint its usually safe to keep the default values of the charge pu mp registers. only if a red led is used (on led7...led9), reset the register bits led7_on_cp =0, led8_on_cp =0 and/or led9_on_cp =0 to improve efficiency. 7. exception: the manual mode switching mode ( cp_mode_switching =11) can override this behavior. table 38. cp_mode_switch register addr: 06h cp_mode_switch register bit bit name default access description 0 led7_on_cp 1b r/w configure if led7 is powered by charge pump 0 led7 is powered by vbat (e.g. red led) 1 led7 is powered from vout 1 led8_on_cp 1b r/w configure if led8 is powered by charge pump 0 led8 is powered by vbat (e.g. red led) 1 led8 is powered from vout 2 led9_on_cp 1b r/w configure if led9 is powered by charge pump 0 led9 is powered by vbat (e.g. red led) 1 led9 is powered from vout 3 cp_max_5v4 0b r/w adjusts the maximum output voltage of the charge pump 0 charge pump vout regulates to 4.5v 1 charge pump vout regulates to maximum 5.4v 4 cp_skip_on 1b r/w allows pulse skip mode of charge pump 0 pulse skip of charge pump is disabled 1 enable pulse skip of charge pump in low load conditions (reduce quiescent current in 1:1.5 mode) 5 cp_auto_reset 1b r/w if all current sources are off, reset the charge pump back to 1:1 mode 0 charge pump keeps last mode 1 reset charge pump to 1:1 if all current sources are off ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 32 - 77 as3665 datasheet, confidential - detailed description general purpose output general purpose output the general purpose output ball can be us ed as an open drain pwm output pad, an adc input or as a general purpose open drain output. the output pad gpo is c ontrolled by register gpo_control : analog to digital converter the as3665 has a built-in 10-bit successive approximation analog-to-digital converter (adc). it is internally supplied by c 2v5 , which is also the full-scale input range (0v defines the adc zero-code). for input signal exceeding c 2v5 (typ. 2.5v) a resistor divider is used to scale the input of the adc converter. table 41 shows the resolution and input ranges. the junction temperature can be calculated according to following formula (adc tempcode is the result of the adc conversion from channel 1h): t junction [oc] = adc toffset - adc tc * adc tempcode (eq 1) table 39. led_control2 register addr: 03h led_control2 register bit bit name default access description 7 gpo_on 0b r/w enable pwm generator driving gpo 0 gpo pwm generator is off 1 gpo pwm generator is enabled table 40. gpo_control register addr: 04h gpo_control register bit bit name default access description 1:0 gpo_mode 00b r/w define operating mode of gpo ball 00 open drain pwm output 01 open drain output of signal gpo_signal 10 don?t use 11 2 gpo_signal 0b r/w status of gpo ball if gpo_mode =01 0 active low 1 tristate or if used for adc table 41. adc input ranges channel pin or signal input range v lsb note 0h pin int/audio_in if used with audio buffer 0.0v - 2.5v na see section audio input on page 34 1h junction temperature adc tempcode -30oc - 125oc adc tc see eq 1 3h-5h int/audio_in, gpo, vbat 0.0v - vbat adc lsb internal voltage divider 6h-fh vout, led1, led2...led9 0.0v - vout adc lsb internal voltage divider ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 33 - 77 as3665 datasheet, confidential - detailed description analog to digital converter the adc is controlled by: the adc result is stored in registers adc<9:3> and adc<2:0> ; a running conversion is identified by result_not_ready : table 42. adc_control register addr: 09h adc_control register bit bit name default access description 3:0 adc_select 0h r/w select adc channel to be converted 0h audio buffer (uses pin int/audio_in and audio input amplifier - see section audio input on page 34 ) 1h adc tempcode 1 1. set temp_sens_on (see page 24) =1 before the measurement 2h don?t use 3h int/audio_in 4h gpo 2 2. set gpo_signal =1 and gpo_mode =01 to switch pad gpo into tristate 5h vbat 6h vout 7h led1 8h led2 9h led3 ah led4 bh led5 ch led6 dh led7 eh led8 fh led9 5 adc_continuous 1b r/w enable adc continuous conversion 0 no continuous conversion 1 adc is continuously converting. if a conversion is finished an interrupt can be sent (register bit adc_eoc on page 37 ) 6 adc_slow 1b r/w select adc conversion time 0 16s adc conversion time 1 32s adc conversion time 7 adc_single_conversion 0b w writing ?1? starts a single adc conversion. if a conversion is finished an interrupt can be sent (register bit adc_eoc ) table 43. adc_msb_result register addr: 0ah adc_msb_result register bit bit name default access description 6:0 adc<9:3> na r adc result bits 9:3 (msbs) ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 34 - 77 as3665 datasheet, confidential - detailed description audio input audio input figure 20. audio input internal circuit the audio input can be used to connect an analog audio signal to the as3665 and do lighting effects dependent on this input signal on pad int/audio_in 8 . the audio processing path is shown in figure 20 : the audio signal is amplified by the input amplifier with an adjustable gain setting to allow different audio input levels. with the a dc the signal is converted into a digital 10 bits signal. after the agc, the data is filtered and then can be used with the sequencer command get adc (see page 67) . the sequencers can then run different filter and proc essing algorithms to obtain the lighting effects. 7 result_not_ready na r indicates end of adc conversion cycle 0 result is ready 1 conversion is running table 44. adc_lsb_result register addr: 0bh adc_lsb_result register bit bit name default access description 2:0 adc<2:0> na r adc result bits 2:0 (lsbs) 8. set int_mode =01 (analog input for ball int/audio_in) and set adc_select =0 (to select audio buffer) table 45. audio_control register addr: 1ch audio_control register bit bit name default access description 0 audio_on 0b r/w enable agc and peak detect for audio processing 0 get adc gets adc value directly 1 get adc uses agc and audio filter -recommended setting if a audio signal is connected to the as3665 table 43. adc_msb_result register (continued) addr: 0ah adc_msb_result register bit bit name default access description ./01 !"##! $ % #& ' !!& ! (# )#* #!#& (( + $# &# as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 35 - 77 as3665 datasheet, confidential - detailed description audio input agc (automatic gain control) the agc is used to ?compress? the input signal and to att enuate very low input amplitude signals (this is performed to ensure no light output for low signals especially for noisy input signals). the agc monitors the input signal amplitude and filters this amplitude with a filter with a short attack time, but a long decay time (decay time depends on the register agc_ctrl ). this amplitude measurement (represented by an integer value from 0 to 15; the decay time of this measurement is controlled by agc_time ) is then used to amplify or attenuate the input signal with one of the following amplification ratios (output to input ratio) ? the cu rve a, b, or c is selected depending on the register agc_ctrl : 1 audio_cmdset 0b r/w modifies the behavior for over/underflow with the sequencer adder and subtract commands 0 a over/underflow rolls over 1 the adder/subtract command saturate at zero and full scale 1 2 audio_buf_on 0b r/w enable audio input buffer 0 off any selection of adc_select possible 1 on adc_select =0 (audio buffer) mandatory 5:3 audio_buf_gain 000b r/w audio input buffer gain setting 000 -12db 001 -6db 010 0db 011 +6db 100 +12db 101 +18db 110 +24db 111 +30db 7:6 reserved 00b r/w reserved - always set to 00b 1. for audio processing always set audio_cmdset =1 table 46. agc gain curves input amplitude agc gain curve a curve b curve c 0 0.0 0.0 0.0 1 7.5 5.0 3.5 2 7.0 4.0 3.0 3 4.5 3.5 2.5 4 3.5 3.0 2.0 5 3.0 2.5 1.5 6 2.5 2.5 1.5 table 45. audio_control register (continued) addr: 1ch audio_control register bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 36 - 77 as3665 datasheet, confidential - detailed description interrupt generator interrupt generator the interrupt generator can send interrupt signals to e.g. the applicat ion processor to identify e.g. the end of pattern or a special event. when a not masked interrupt (register interrupt_mask ) is triggered the int/audio_in 9 pin is pulled low until the interrupt is reset by the i 2 c interface. interrupt are readout by the interrupt_status register; pending interrupts are reset by writing back ?1? to the register bit in interrupt_status which should be reset: following procedure to readout the interrupt is recommended: 7 2.0 2.0 1.5 8 2.0 2.0 1.5 9 1.5 2.0 1.5 10 1.5 1.5 1.0 11 1.5 1.5 1.0 12 1.0 1.5 1.0 13 1.0 1.0 1.0 14 1.0 1.0 1.0 15 1.0 1.0 1.0 table 47. audio_agc register addr: 1dh audio_agc register bit bit name default access description 2:0 agc_ctrl 000b r/w control agc transfer function 000 agc off (bypass) 001 attenuate low amplitude signals otherwise linear response (to remove e.g. noise) 010 agc curve a; slow decay of amplitude detection 011 agc curve a; fast deca y of amplitude detection 100 agc curve b; slow decay of amplitude detection 101 agc curve b; fast deca y of amplitude detection 110 agc curve c; slow decay of amplitude detection 111 agc curve c; fast deca y of amplitude detection 4:3 agc_time 00b r/w agc amplitude detection decay time; minimum duration from min. gain to max. gain 00 460ms 01 920ms 10 1840ms 11 3670ms 9. the output should be enabled by setting register int_mode =00 (open drain interrupt output) table 46. agc gain curves input amplitude agc gain curve a curve b curve c ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 37 - 77 as3665 datasheet, confidential - detailed description interrupt generator 1. readout register interrupt_status 2. write back the readout value in (1) to interrupt_status - this automatically resets all readout interrupts (and no interrupts can be lost) interrupts can be enabled / disabled individually by the interrupt_mask register (if an interrupt is masked, it will not pull- down the pin int/audio_in): table 48. interrupt_status register addr: 0ch interrupt_status register bit bit name default access description 0 int1 0r/w sequencer 1 has triggered an interrupt see end/interrupt command on page 54 0 no interrupt 1 interrupt pending 1 int2 0r/w sequencer 2 has triggered an interrupt see end/interrupt command on page 54 0 no interrupt 1 interrupt pending 2 int3 0r/w sequencer 3 has triggered an interrupt see end/interrupt command on page 54 0 no interrupt 1 interrupt pending 3 no_extclock_detected 0r/w monitor external clock detection on pin clk32k - see clock generation on page 14 0 external clock is ok or internal clock is selected 1 external clock is selected and no external clock is detected 4 init_ready_int 0r/w see device operating mode on page 12 0 initialization of the internal data of as3665 is ongoing 1 initialization of the as3665 is finished 5 adc_eoc 0r/w adc end of conversion - see analog to digital converter on page 32 0 adc not started or conversion ongoing 1 adc has finished a conversion 6 ov_temp 0r/w see temperature supervision on page 39 0 temperature ok 1 overtemperature detected table 49. interrupt_mask register addr: 0dh interrupt_mask register bit bit name default access description 0 int1_masked 1r/w 0no mask 1 int1 is masked 1 int2_masked 1r/w 0no mask 1 int2 is masked ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 38 - 77 as3665 datasheet, confidential - detailed description interrupt generator the interrupt output pad int/audio_in is controlled by register gpo_control : 2 int3_masked 1r/w 0no mask 1 int3 is masked 3 no_extclock_detected_m asked 1r/w 0no mask 1 no_extclock_detected is masked 4 init_ready_int_masked 1r/w 0no mask 1 init_ready_int is masked 5 adc_eoc_masked 1r/w 0no mask 1 adc_eoc is masked 6 ov_temp_masked 1r/w 0no mask 1 ov_temp is masked table 50. gpo_control register addr: 04h gpo_control register bit bit name default access description 4:3 int_mode 00b r/w define operating mode of int/audio_in ball 00 open drain output of interrupt status 01 push/pull output of signal int_signal 10 analog input - use for audio input (see page 34) or analog to digital converter (see page 32) 11 5 int_signal 0b r/w status of int/audio_in ball if int_mode =01 0 active low 1 active high (vbat) 7 int_on_trig 0b r/w interrupt output selection flag 0 interrupt status is available on ball int/audio_in (if int_mode =00) 1 interrupt status is available on ball trig 1 1. set int_on_trig =1 if the ball int/audio_in is used for audio and/or adc and an interrupt output is required; the ball trig is then used as the interrupt open drain output table 49. interrupt_mask register (continued) addr: 0dh interrupt_mask register bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 39 - 77 as3665 datasheet, confidential - detailed description trigger pin trig trigger pin trig trigger commands can be sent by the internal sequencers to any other sequencer and or to/from the pin trig using the sequencer command trigger (see page 55) . the pin trig is active low, requires and external pullup resistor and the input should be enabled by setting trig_input_on =1. sent external trigger commands ar e three 32.768khz clock cycles (see clock generation on page 14 ) long and received external triggers shall be longer than two clock cycles. during sending of an external trigger, the trig input is blocked. note: if two as3665 devices send an external trigger at the exactly same time, the trigger command might get lost. therefore it is recommended that only one as3665 in a system should send trigger command and all other devices only receive trigger commands. it is recommend to configure trig_input_on before program execution as changing trig_input_on during pro- gram execution can set a trigger pulse to the program. led test to test the led in the production line, force a test current through the to be tested led. measure the voltage on the led (by setting adc_select (see page 33) to the led channel led1...led9). if the voltage on the led is within the specified parameters for the led, the led is working properly. temperature supervision the temperature supervision protect the as3665 against overte mperature - in case of ov ertemperature the as3665 is reset (and therefore the charge pump is set back to 1:1 mo de and all current sources are switched off). it is recom- mended to leave the temperature supervision always enabled (register bit ov_temp_on , default on): table 51. exec_mode register addr: 01h exec_mode register bit bit name default access description 7 trig_input_on 0b r/w enable external trigger input on pin trig 0 external trigger disabled 1 external trigger enabled table 52. supervision register addr: 08h supervision register bit bit name default access description 0 ov_temp_on 1 1. always leave ov_temp_on set. 1h r/w overtemperature protection 0 overtemperature protection disabled 1 overtemperature protection enabled 1 ov_temp_status 0h r/w overtemperature protection triggered 0 no overtemperature detected 1 overtemperature detected ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 40 - 77 as3665 datasheet, confidential - detailed description i 2 c mode serial data bus i 2 c mode serial data bus the as3665 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. a master device that generates the serial clock (s cl), controls the bus access, and generates the start and stop conditions must control the bus. the as3665 operates as a slave on the i 2 c bus. within the bus specifications a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the as3665 works in both modes. connections to the bus are made through the open-drain i/o lines sda and scl. i 2 c address selection the slave address can be selected depending on the external resistor r addr connected to the pin addr. the actual address for reading and writing is selected according to table 53 . the following bus protocol has been defined ( figure 21 ): data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy both data and clock lines remain high. start data transfer a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line mu st be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and te rminated with a stop condition. the number of data bytes transferred between start and stop conditions are not li mited, and are determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. table 53. i 2 c address selection r addr i 2 c address 1 for 1. this i 2 c address has 8 bits and includes the r/w flag (lsb). if a 7 bits address is required, use the 7 msbs. writing reading > 320k : (leave r addr open) 80h 81h 320k : 82h 83h 160k : 84h 85h 80k : 86h 87h 40k : 88h 89h 20k : 8ah 8bh 10k : 8ch 8dh 0k : (short to gnd) 8eh 8fh ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 41 - 77 as3665 datasheet, confidential - detailed description i 2 c mode serial data bus acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line duri ng the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 21. data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitt ed by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2. data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all rece ived bytes other than the la st byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with t he most significant bit (msb) first. the as3665 can operate in the following two modes: 1. slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the begin- ning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see figure 22) . the slave address byte is the first byte received after the master generates the start condition. the slave address by te contains the 7-bit as3665 address, which is 1000xxx 10 , followed by the direction bit (r/w), which, for a write, is 0. 11 after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. after the as3665 acknowledges the slave address + write bit, the master transmits a register address to the as3665. this sets the register pointer on the as3665. the master may then transmit zero or more bytes of data (if more than one data byte is written 10.?xxx? depends on the external resistor r addr used; see i 2 c address selection on page 40 11.the address for writing to the as3665 is 8xh = 1000xxx0b - see table 53 slave address acknowledgement signal from receiver acknowledgement signal from receiver repeated if more bytes are transferred stop condition or repeated start condition start condition scl sda msb r/w direction bit ack 1 2 6 78 9 1 2 3-8 89 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 42 - 77 as3665 datasheet, confidential - detailed description i 2 c mode serial data bus see also blockwrite/read boundaries on page 43 ), with the as3665 acknowledging each byte received. the address pointer will increment after each data byte is tr ansferred. the master generates a stop condition to terminate the data write. 2. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that t he transfer direction is reversed. serial data is transmit- ted on sda by the as3665 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer ( figure 23 and figure 24 ). the slave address byte is the first byte received after the master generates a start condition. the slave address byte contains the 7-bit as3665 address, which is 1000xxx, followed by the di rection bit (r/w), whic h, for a read, is 1. 12 after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. the as3665 then begins to transmit data starting with the register addre ss pointed to by the register pointer (if more than one data byte is read see also blockwrite/read boundaries on page 43 ). if the register point er is not written to before the initiation of a read mode the first address that is read is the la st one stored in the register pointer. the as3665 must receive a ?not acknowledge? to end a read. figure 22. data write - slave receiver mode figure 23. data read (from current po inter location) - slave transmitter mode 12.the address for read mode from the as3665 is 8xh+1 = 1000xxx1b - see table 53 s 1000xxx 0 a xxxxxxxx a aa xxxxxxxx xxxxxxxx a xxxxxxxx p www.austriamicrosystems.com revision 1.0.2 43 - 77 as3665 datasheet, confidential - detailed description i 2 c mode serial data bus figure 24. data read (write pointer, then read) - slave receive and transmit blockwrite/read boundaries if more than a single data-byte is written to or r ead from the as3665 the address boundaries described in table 54 shall not be crossed 13 : program downloading there are two possibilities to download programs - program direct access and program download using page select 14 : program direct access wring to i 2 c register program_direct_access allows direct access to the complete internal program memory using a single blockwrite command. program downloading starts fr om address www.austriamicrosystems.com revision 1.0.2 44 - 77 as3665 datasheet, confidential - detailed description i 2 c mode serial data bus figure 25. program write - slave receiver mode program download using page select first the register page_select is set to the program page, which should be accessed. then the program page (part of or full page) can be downloaded to the registers cmd_0_msb , cmd_0_lsb , cmd_1_msb , cmd_1_lsb ... cmd_f_msb , cmd_f_lsb (i 2 c registers area 60h to 7fh) 15 . table 55. page_select register addr: 5fh page_select register bit bit name default access description 2:0 page_select 000b r/w selects program page for download 000 page 0 - addr 00h-0fh 001 page 1 - addr 10h-1fh 010 page 2 - addr 20h-2fh 011 page 3 - addr 30h-3fh 100 page 4 - addr 40h-4fh 101 page 5 - addr 50h-5fh 110 don?t use 111 don?t use 15.setting page_select and writing of the program content shall use separate i 2 c commands (see blockwrite/ read boundaries on page 43) s 1000xxx 0 a 11111110 a a xxxxxxxx www.austriamicrosystems.com revision 1.0.2 45 - 77 as3665 datasheet, confidential - programming concept 9 programming concept the internal structure for the sequencers, memory, pwm generator and i 2 c map is shown in figure 26 : figure 26. internal sequencers structure the as3665 includes three program controlled sequencers oper ating on the internal memory. each of these sequenc- ers can be dynamically mapped to any of the pwm generator. each of the pwm controllers has following structure: figure 27. pwm controllers @ ! " #! $ % & %' & * ' & * ' & * ' % + % + % + as3665 ! ! "#$ $% &' ! ( $% $ !)* +% ! , , -" -#. / , "#% "#0 &' ! , as3665 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 46 - 77 as3665 datasheet, confidential - programming program execution and debugging it uses the command delivered by the sequencers, executes them, converts th e data from linear to logarithmic repre- sentation add color correction and a master value. this sign al is then feed into the act ual pwm generator which con- trols the led current source. program execution and debugging following steps are required for the setup of the as3665 and execution of a program 1. the as3665 operating mode should be standby or active - see device operating mode on page 12 2. set the led currents - see current sources on page 15 3. the charge pump usually can be left at their default setting - see cp setting application hint on page 31 4. download of program: see program downloading on page 43 . 5. write the program start addresses to registers start_addr1 , start_addr2 and start_addr3 16 6. initialize the program counters pc1 ... pc3 by setting p1_en =01, p2_en =01 and p3_en =01. the program exe- cution is automatically enabled ( p1_en ... p3_en is set to 10 by the as3665). 7. set as3665 operating mode to active by setting chip_en =1 - see device operating mode on page 12 8. execute the program by setting p1_mode =10, p2_mode =10 and p3_mode =10 sequencers can be stopped by setting p1_mode ... p3_mode =00 (hold). single step debugging is achieved by setting p1_mode ... p3_mode =01. 17 the program counter can be controller ei ther by direct writing to registers pc1 ... pc3 or reset with p1_en ... p3_en as shown above 9. use as3665 standby mode (set chip_en =0) to stop all programs and disable all current sources 16.assuming all three sequencers are actually used for the program. 17.the demoboard software simplifies the debugging using a graphical user interface. table 56. exec_enable register addr: 00h exec_enable register bit bit name default access description 1:0 p1_en 00b r/w execution enable for sequencer 1 00 sequencer 1 is disabled 1 01 reload program counter and enable: set pc1 to start_addr1 , initialize sequencer 1 internal loop counters then set p1_en =10 (run) 10 execute sequencer co mmands as defined by p1_mode 11 don?t use 3:2 p2_en 00b r/w execution enable for sequencer 2 00 sequencer 2 is disabled 1 01 reload program counter and enable: set pc2 to start_addr2 , initialize sequencer 2 internal loop counters then set p2_en =10 (run) 10 execute sequencer co mmands as defined by p2_mode 11 don?t use ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 47 - 77 as3665 datasheet, confidential - programming program execution and debugging the exec_mode register defines the sequencer exec uting mode (e.g. single step or run): 5:4 p3_en 00b r/w execution enable for sequencer 3 00 sequencer 3 is disabled 1 01 reload program counter and enable: set pc3 to start_addr3 , initialize sequencer 3 internal loop counters then set p3_en =10 (run) 10 execute sequencer co mmands as defined by p3_mode 11 don?t use 1. if all sequencers are switched off ( p1_en =00, p2_en =00 and p3_en =00), led1_on ... led9_on control the oper- ation of the leds - see current sources on page 15 table 57. exec_mode register addr: 01h exec_mode register bit bit name default access description 1:0 p1_mode 00b r/w execution mode for sequencer 1 if p1_en =10 00 hold - finish current instruction and stop. 01 step - execute one instruction at pc1 and increment pc1 then reset p1_mode (hold) 10 run - start execution from pc1 11 step in place - execute one instruction at pc1 but don?t increment pc1 then reset p1_mode (hold) 3:2 p2_mode 00b r/w execution mode for sequencer 2 if p2_en =10 00 hold - finish current instruction and stop. 01 step - execute one instruction at pc2 and increment pc2 then reset p2_mode (hold) 10 run - start execution from pc2 11 step in place - execute one instruction at pc2 but don?t increment pc2 then reset p2_mode (hold) 5:4 p3_mode 00b r/w execution mode for sequencer 3 if p3_en =10 00 hold - finish current instruction and stop. 01 step - execute one instruction at pc3 and increment pc3 then reset p3_mode (hold) 10 run - start execution from pc3 11 step in place - execute one instruction at pc3 but don?t increment pc3 then reset p3_mode (hold) table 56. exec_enable register (continued) (continued) addr: 00h exec_enable register bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 48 - 77 as3665 datasheet, confidential - programming sequencers the program memory areas are setup using start_addr1 ... start_addr3 : the actual program execution of the seque ncers is defined by the program counters pc1 ... pc3 : sequencers all three sequences are autonomous program execut ion unit executing the commands described in sequencer com- mands table (see page 66) . programs are downloaded, star ted and stopped as described in program downloading (see page 43) . the output of these sequencers is used for the pwm generator defined by so called mux tables: table 58. start_addr1 register addr: b0h start_addr1 register bit bit name default access description 7:0 start_addr1 00h r/w sequencer 1 start of program table 59. start_addr2 register addr: b1h start_addr2 register bit bit name default access description 7:0 start_addr2 00h r/w sequencer 2 start of program table 60. start_addr3 register addr: b2h start_addr3 register bit bit name default access description 7:0 start_addr3 00h r/w sequencer 3 start of program table 61. seq1_pc register addr: b4h seq1_pc register bit bit name default access description 7:0 pc1 00h r/w sequencer 1 program counter table 62. seq2_pc register addr: b5h seq2_pc register bit bit name default access description 7:0 pc2 00h r/w sequencer 2 program counter table 63. seq3_pc register addr: b6h seq3_pc register bit bit name default access description 7:0 pc3 00h r/w sequencer 3 program counter ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 49 - 77 as3665 datasheet, confidential - programming sequencers mux tables - assignments of sequencers to channels the mux tables are setup during a program executio n dynamically with the foll owing sequencer commands: - mux set start address (see page 55) and mux set end address (see page 56) define a memory region where the mux tables is operating ( mux next address or mux previous address ). mux set start address automatically loads the mux for this sequencer with the c ontent of the memory of ?start address?. - mux next address (see page 56) and mux previous address (see page 57) increase (or decrease) the mux pointer by one and load the mux of this sequencer with th e memory content the pointer is addressing. the mux pointer is kept within range defined by mux set start address and mux set end address . - mux set ptr (see page 58) sets the mux pointer to a address defined by a displacement and mux set start address - mux select led (see page 56) selects a single pwm output (single led) where this sequencer is connected to. this is useful for simple sequencer - pwm connect ions without requiring to setup a dedicated mux table. - mux clear (see page 56) clears the mux of this sequencer (no pwm channels are selected anymore). the sequencer can operat e in two operating modes: 1. pwm mode - this is the standard operating mode; the sequencer directly controls any of the pwm generators. this is the default operating mode. 2. ratiometric mode - the sequencer controls one or more of the faders ( fader1 (see page 23) , fader2 and/or fader3 ). the fader can control general led brightness (c onfigurable to control any number of leds) - see cur- rent sources (see page 15) . 18 the ratiometric mode is ent ered with the command mux set rm (see page 66) or mux fade (see page 66) . the as3665 returns to pwm mode with the command mux reset rm . 19 the sequencer are connected to the pwm generators and faders according to figure 28 (the 16 bits are the content of the memory register, the mux pointer is pointing to. a ?1? con nects the sequencer to this ou tput, a ?0? disconnects this output): figure 28. mux table connections variables the as3665 includes four variables ra, rb, rc and rd. these variables can read and written by the i 2 c interface and in parallel read and written by the sequencers 20 . using the variables, programs can be controlled by a single i 2 c com- mands. sequencers can use these variables for internal calculations, for communication between the sequencers and to communicate to the i 2 c controller. 18.the mux tables share the same start address set by mux set start address but have separate current addresses and end addresses set by mux set end address 19.use only the highest (in order 1,2,3) sequencers for ratiometric mode (e.g. seq1 pwm, seq2 ratiometric but not seq3 for pwm mode at the same time) 20.variable rd is read/writable by i 2 c but only readable by the sequencers. ! "! #$! ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 50 - 77 as3665 datasheet, confidential - programming sequencers there are two local variables (local to each sequencer): ra and rb - each sequencer sees its own variable: there are two global variables: rc and rd - these are shared between all sequencers: table 64. variable_a1 register addr: b8h variable_a1 register bit bit name default access description 7:0 var_a1 00h r/w sequencer 1 local variable ra table 65. variable_a2 register addr: b9h variable_a2 register bit bit name default access description 7:0 var_a2 00h r/w sequencer 2 local variable ra table 66. variable_a3 register addr: bah variable_a3 register bit bit name default access description 7:0 var_a3 00h r/w sequencer 3 local variable ra table 67. variable_b1 register addr: bch variable_b1 register bit bit name default access description 7:0 var_b1 00h r/w sequencer 1 local variable rb table 68. variable_b2 register addr: bdh variable_b2 register bit bit name default access description 7:0 var_b2 00h r/w sequencer 2 local variable rb table 69. variable_b3 register addr: beh variable_b3 register bit bit name default access description 7:0 var_b3 00h r/w sequencer 3 local variable rb table 70. variable_c register addr: bbh variable_c register bit bit name default access description 7:0 var_c 00h r/w global variable rc - variable available for all sequencers table 71. variable_d register addr: 0fh variable_d register bit bit name default access description 7:0 var_d 00h r/w global variable rd - variable available for all sequencers ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 51 - 77 as3665 datasheet, confidential - programming audio processing audio processing use austriamicrosystems sample codes for audio processing. sequencer commands ramping of pwm(s) is achieved by the ramp/wait command shown in table 72 . the selected channels are chosen by mux tables - assignments of sequencers to channels on page 49 . this command also can be used to wait for a defined time in the program execution (if number of increments = 0). with the set pwm command pwm(s) (pwm channels are connec ted to a sequencer as shown in section mux tables - assignments of sequencers to channels on page 49 ) can be immediately forced to a value: table 72. ramp/wait command ramp/wait command ramps the pwm of the selected pwm generator up or down; if the number of increments is zero, it simply waits name bits bitname parameter description ramp/wait compiler syntax: rmp, prescale, step time, sign, number of increments; d15 0 d14 prescale 0 each step has 16 clock cycles (typ. 0.49ms at 32768hz) 1 each step has 512 clock cycles (typ. 15.6ms at 32768hz) the clock generation is described in section clock generation on page 14 d13:d9 step time 1-31 duration between single increments/decrements e.g. if step time=8, prescale=0 , sign=0, the duration between every increment is typically 0.49ms*8 = 3.92ms d8 sign 0 ramp up, always increment by 1; 255 is maximum value 1 ramp down, always decrement by 1; 0 is minimum value d7:d0 number of increments 0 wait for duration defined by prescale and step time 1-255 number of actual cycles in a single ramp command (e.g. 255 defines a full scale ramp) table 73. set pwm command set pwm command force pwm name bits bitname parameter description set pwm compiler syntax: spw, pwm value; d15:d8 01000000b (40h) d7:d0 pwm value 0-255 actual pwm value used: 0...off 255...full scale ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 52 - 77 as3665 datasheet, confidential - programming sequencer commands ramping of pwm(s) dependent on variables is achieved by the ramp with variable command shown in table 74 . this command also can be used to wait for a defined time in the program execution (if number of increments = 0). table 74. ramp with variable command ramp with variable command ramps the pwm of the selected pwm generator up or down; if the number of increments is zero, it simply waits name bits bitname parameter description ramp with variable compiler syntax: rwv, prescale, sign, variable for step, variable for number of increments; d15:d6 10000100_ 00b d5 prescale 0 each step has 16 clock cycles (typ. 0.49ms at 32768hz) 1 each step has 512 clock cycles (typ. 15.6ms at 32768hz) the clock generation is described in section clock generation on page 14 d4 sign 0 ramp up, always increment by 1; 255 is maximum value 1 ramp down, always decrement by 1; 0 is minimum value d3:d2 variable for step the content of the variable defines the duration between single increments/decrements; e.g. if va riable rx=8, prescale=0, sign=0, the duration between every increment is typically 0.49ms*8 = 3.92ms 0 variable ra 1 variable rb 2 variable rc 3 variable rd d1:d0 variable for number of increments if the content of the variable rx is 0 then wait for duration defined by prescale and d3:d2 1-255 then it defines the number of actual cycles in a single ramp command (e.g. 255 defines a full scale ramp) 0 variable ra 1 variable rb 2 variable rc 3 variable rd ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 53 - 77 as3665 datasheet, confidential - programming sequencer commands with the set pwm to variable command pwm(s) (pwm channels are connect ed to a sequencer as shown in section mux tables - assignments of sequencers to channels on page 49 ) can be immediately forced to a value of a variable: with the goto start command the program counter of the sequencer is reset to its start value: with the branch command loops can be implemented. loops can be nested without limits: with the branch with variable command loops can be implemented. the number of loops are defined by a variable. table 75. set pwm to variable command set pwm to variable command force pwm name bits bitname parameter description set pwm to variable compiler syntax: spv, variable; d15:d2 10000100_ 011000b d1:d0 variable the content of the variable is used to set the pwm value: 0...off 255...full scale 0 variable ra 1 variable rb 2 variable rc 3 variable rd table 76. goto start command goto start command name bits bitname parameter description goto start compiler syntax: gts; d15:d0 00000000_ 00000000b (0000h) set sequencer program counter to start address if sequencer 1 then pc1 = start_addr1 if sequencer 2 then pc2 = start_addr2 if sequencer 3 then pc3 = start_addr3 table 77. branch command branch command name bits bitname parameter description branch compiler syntax: brn, loop count, step number; d15:d13 010b d12:d7 loop count 0 infinite loops 1-63 1 to 63 loops d6:d0 step number 0-127 jump to ?step number? for ?loop count? times; sets the pc of this sequencer = ?step number?; in the compiler ?step number? can be defined by a label ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 54 - 77 as3665 datasheet, confidential - programming sequencer commands loops can be nested without limits: with the end/interrupt command command program execution is stopped and optionally an interrupt is sent: with the trigger command internal (between sequencers) and external (between several as3665) synchronization is table 78. branch with variable command branch with variable command name bits bitname parameter description branch with variable compiler syntax: brv, step number, variable; d15:d9 1000011b d8:d2 step number 0-127 jump to ?step number? for ?variable? times; sets the pc of this sequencer = ?step number?; in the compiler ?step number? can be defined by a label d1:d0 variable the content of the variable defines the number of loops performed (0=infinite) 0 variable ra 1 variable rb 2 variable rc 3 variable rd table 79. end/interrupt command command end/interrupt command command name bits bitname parameter description end/interrupt command compiler syntax: end, int, reset; d15:d13 101b d12 int 0 no interrupt is sent 1 send an interrupt (see interrupt generator on page 36) and disable this sequencer e.g. for sequencer 1, int3 =1 and p1_en (see page 46) = 00 d11 reset 0 program counter is incremented by 1 1 program counter is reset to start address e.g. for sequencer 1, pc1 = start_addr1 d10:d0 000_ 00000000b stop program execution by resetting px_mode e.g. for sequencer 1, p1_mode (see page 47) = 00 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 55 - 77 as3665 datasheet, confidential - programming sequencer commands possible (see trigger pin trig on page 39) : with the mux set start address and mux set end address commands the memory area for the multiplexer between the sequencers and the output pwm generators are initialized. (see mux tables - assignments of sequencers to chan- nels on page 49) : table 80. trigger command trigger command name bits bitname parameter description trigger compiler syntax: trg, wait trigger channels, send trigger channels; d15:d13 111b wait for trigger from... d12 ext trig 0 no trigger 1 wait for external trigger from pin trig 1 1. set trig_input_on (see page 39) =1 to enable the input. d11:d10 xxb d9 ch3 0 no trigger 1 wait for trigger from sequencer 3 d8 ch2 0 no trigger 1 wait for trigger from sequencer 2 d7 ch1 0 no trigger 1 wait for trigger from sequencer 1 send trigger to... d6 ext trig 0 no trigger 1 send trigger to pin trig d5:d4 xxb d3 ch3 0 no trigger 1 send trigger to sequencer 3 d2 ch2 0 no trigger 1 send trigger to sequencer 2 d1 ch1 0 no trigger 1 send trigger to sequencer 1 d0 xb table 81. mux set start address command mux set start address command name bits bitname parameter description mux set start address compiler syntax: mss, ram address; d15:d7 10011100 0b d6:d0 ram address 0-127 sets the multiplexer start addre ss to ?ram address?. after the next command is executed the multiplexer for this sequencer is initialized by the content of this ?ram address?. ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 56 - 77 as3665 datasheet, confidential - programming sequencer commands a similar command is used to set the multiplexer memory area end address: with the mux select led command the sequencer can be simply connect ed to a single output (if more than one out- put should be controlled by one sequencer see mux tables - assignments of sequencers to channels (see page 49) ): with the mux clear command the multiplexer tables are initialized (see page 49) : with the mux next address command the mux pointer can be moved down in the mux table (see page 49) : table 82. mux set end address command mux set end address command name bits bitname parameter description mux set end address compiler syntax: mse, ram address; d15:d7 10011100 1b d6:d0 ram address 0-127 sets the multiplexer end address to ?ram address?. table 83. mux select led command mux select led command name bits bitname parameter description mux select led compiler syntax: msl, led select; d15:d7 10011101 0b d6:d0 led select 1-9 connect this sequencer to a single output defined by ?led select?; e.g. 3 selects output led3 table 84. mux clear command mux clear command name bits bitname parameter description mux clear compiler syntax: mcl; d15:d0 10011101 00000000b (9d00h) clear the mux table (this sequencer is not connected to any output) table 85. mux next address command mux next address command name bits bitname parameter description mux next address compiler syntax: mna; d15:d0 10011101 10000000b (9d80h) increase the mux pointer by one; if the address would be above the address defined by mux set end address , reset the mux pointer to the address defined by mux set start address ; load the mux with the content of this memory address ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 57 - 77 as3665 datasheet, confidential - programming sequencer commands with the mux previous address command the mux pointer can be moved up in the mux table (see page 49) : with the mux set rm and mux reset rm command the sequencer can be configured for ratiometric mode or pwm mode: mux fade is used to set the sequencer in ratiometric mode an d configure the faders whic h are connected to this sequencer with one single command - no additional mux tables are required: table 86. mux previous address command mux previous address command name bits bitname parameter description mux previous address compiler syntax: mpa; d15:d0 10011101 11000000b (9d8ch) decrease the mux pointer by one; if the address would be below the address defined by mux set start address , reset the mux pointer to the address defined by mux set end address ; load the mux with the content of this memory address table 87. mux set rm command mux set rm command name bits bitname parameter description mux set rm compiler syntax: srm; d15:d0 10011101 00100000b (9d20h) set sequencer ratiometric mode - see mux tables - assignments of sequencers to channels on page 49 table 88. mux reset rm command mux reset rm command name bits bitname parameter description mux reset rm compiler syntax: rrm; d15:d0 10011101 01000000b (9d40h) reset sequencer ratiometric mode (= pwm mode) - see mux tables - assignments of sequencers to channels on page 49 table 89. mux fade command mux fade command name bits bitname parameter description mux fade compiler syntax: mxf, www.austriamicrosystems.com revision 1.0.2 58 - 77 as3665 datasheet, confidential - programming sequencer commands mux set ptr set the mux pointer to an address www.austriamicrosystems.com revision 1.0.2 59 - 77 as3665 datasheet, confidential - programming sequencer commands table 92. jge (jump >=) command jge (jump >=) command name bits bitname parameter description jge (jump >=) compiler syntax: jge, instructions skipped, variable 1, variable 2; d15:d9 1000101b d8:d4 instructions skipped 0-31 defines the number of instructions skipped, if variable1 >= variable2 pc = pc + ?instructions skipped? d3:d2 variable 1 0 variable1 = ra 1 variable1 = rb 2 variable1 = rc 3 variable1 = rd d1:d0 variable 2 0 variable2 = ra 1 variable2 = rb 2 variable2 = rc 3 variable2 = rd table 93. jl (jump <) command jl (jump <) command name bits bitname parameter description jl (jump <) compiler syntax: jl, instructions skipped, variable 1, variable 2 d15:d9 1000110b d8:d4 instructions skipped 0-31 defines the number of instructions skipped, if variable1 < variable2 pc = pc + ?instructions skipped? d3:d2 variable 1 0 variable1 = ra 1 variable1 = rb 2 variable1 = rc 3 variable1 = rd d1:d0 variable 2 0 variable2 = ra 1 variable2 = rb 2 variable2 = rc 3 variable2 = rd ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 60 - 77 as3665 datasheet, confidential - programming sequencer commands variable can be initialized to a constant value by the command ld (load) : table 94. jne (jump <>) command jne (jump <>) command name bits bitname parameter description jne (jump <>) compiler syntax: jne, instructions skipped, va riable 1, variable 2 d15:d9 1000111b d8:d4 instructions skipped 0-31 defines the number of instructions skipped, if variable1 <> variable2 (not equal) pc = pc + ?instructions skipped? d3:d2 variable 1 0 variable1 = ra 1 variable1 = rb 2 variable1 = rc 3 variable1 = rd d1:d0 variable 2 0 variable2 = ra 1 variable2 = rb 2 variable2 = rc 3 variable2 = rd table 95. ld (load) command ld (load) command name bits bitname parameter description ld (load) compiler syntax: ld ta rget variable, value; d15:d12 1001b (9h) d11:d10 target variable 0 set ra = value 1 set rb = value 2 set rc = value 3 don?t use d9:d8 00b d7:d0 value 0-255 value ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 61 - 77 as3665 datasheet, confidential - programming sequencer commands a constant value can be added to a variable with the command add number : variable are added together with the command add variable : table 96. add number command add number command name bits bitname parameter description add number compiler syntax: adn, target variable, value; d15:d12 1001b (9h) d11:d10 target variable 0 set ra = ra + value 1 set rb = rb + value 2 set rc = rc + value 3 don?t use d9:d8 01b d7:d0 value 0-255 value table 97. add variable command add variable command name bits bitname parameter description add variable compiler syntax: adv, target vari able, variable 1, variable 2; d15:d12 1001b (9h) d11:d10 target variable 0 set ra = variable1 + variable2 1 set rb = variable1 + variable2 2 set rc = variable1 + variable2 3 don?t use d9:d4 110000b d3:d2 variable 1 0 variable1 = ra 1 variable1 = rb 2 variable1 = rc 3 variable1 = rd d1:d0 variable 2 0 variable2 = ra 1 variable2 = rb 2 variable2 = rc 3 variable2 = rd ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 62 - 77 as3665 datasheet, confidential - programming sequencer commands a constant value can be subtracted from a variable with the command sub number : variable are subtracted with the command sub variable : audio commands austriamicrosystems provides audio programs to control light depending on an audio input as a starting point for an actual implementation. due to the complexity of these pr ograms it is recommend to use the demos and modify the demo codes accordingly. table 98. sub number command sub number command name bits bitname parameter description sub number compiler syntax: sbn, ta rget variable, value; d15:d12 1001b (9h) d11:d10 target variable 0 set ra = ra - value 1 set rb = rb - value 2 set rc = rc - value 3 don?t use d9:d8 10b d7:d0 value 0-255 value table 99. sub variable command sub variable command name bits bitname parameter description sub variable compiler syntax: sbv, target variable, variable 1, variable 2; d15:d12 1001b (9h) d11:d10 target variable 0 set ra = variable1 - variable2 1 set rb = variable1 - variable2 2 set rc = variable1 - variable2 3 don?t use d9:d4 110001b d3:d2 variable 1 0 variable1 = ra 1 variable1 = rb 2 variable1 = rc 3 variable1 = rd d1:d0 variable 2 0 variable2 = ra 1 variable2 = rb 2 variable2 = rc 3 variable2 = rd ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 63 - 77 as3665 datasheet, confidential - programming sequencer commands with the command get adc , data can be fetched from the audio filter ( see audio input on page 34 ): memory operation command - load/store sram table 100. get adc command get adc command name bits bitname parameter description get adc compiler syntax: get, target variable; d15:d4 10001010_ 0010b (8a2h) d3:d0 target variable 0h set ra = value from adc or filter 5h set rb = value from adc or filter ah set rc = value from adc or filter fh set rd = value from adc or filter other values don?t use table 101. load sram command load sram command name bits bitname parameter description load sram compiler syntax: lds, r/ w, source/target variable; d15:d9 1000_111b (87h) d8 r/w load from or store to sram (register sram0 , sram1 ... sram15 ) 0 read from sram: sram -> target variable 1 write to sram: source variable -> sram d7:d4 sram address define sram address register to load from or store to 0 sram_0 1 sram_1 ... ... f sram_15 d3:d0 source/target variable set source variable for read or target variable for write 0h ra 5h rb ah rc fh rd other values don?t use ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 64 - 77 as3665 datasheet, confidential - programming sequencer commands logical operation commands or command provides a binary or between variables: and command provides a binary and between variables: table 102. or command or command name bits bitname parameter description or compiler syntax: or, input variable, output variable; d15:d9 1000101b d8:d7 input variable 0ra 1rb 2rc 3rd d6:d4 001b d3:d0 output variable 0h set ra = ra or 5h set rb = rb or ah set rc = rc or fh set rd = rd or other values don?t use table 103. and command and command name bits bitname parameter description and compiler syntax: and, input variable, output variable; d15:d9 1000110b d8:d7 input variable 0ra 1rb 2rc 3rd d6:d4 001b d3:d0 output variable 0h set ra = ra and 5h set rb = rb and ah set rc = rc and fh set rd = rd and other values don?t use ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 65 - 77 as3665 datasheet, confidential - programming sequencer commands shift commands shift left variable shift a variable left by 1 (multiply by 2) - if the result exceeds 255, 255 is used as result: shift right variable shifts a variable right by 1 (divide by 2, rounded to 0): table 104. shift left command shift left command name bits bitname parameter description shift left compiler syntax: sl, input variable, output variable; d15:d9 1000101b d8:d7 input variable 0ra 1rb 2rc 3rd d6:d4 000b d3:d0 output variable 0h set ra = * 2 5h set rb = * 2 ah set rc = * 2 fh set rd = * 2 other values don?t use table 105. shift right command shift right command name bits bitname parameter description shift right compiler syntax: sr, input variable, output variable; d15:d9 1000110b d8:d7 input variable 0ra 1rb 2rc 3rd d6:d4 000b d3:d0 output variable 0h set ra = / 2 5h set rb = / 2 ah set rc = / 2 fh set rd = / 2 other values don?t use ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 66 - 77 as3665 datasheet, confidential - sequencer commands table sequencer commands 10 sequencer commands table table 106. sequencer commands table command d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 see page ramp/wait 0 pres cale step time sign number of increments 51 set pwm 01000000 pwm value 51 ramp with variable 1000010000 pres cale sign variable for step variable increment 52 set pwm to variable 10000100011000variable 53 goto start 0000000000000000 53 branch 1 0 1 loop count step number 53 branch with variable 1 0 0 0 0 1 1 step number variable 54 end/interrupt command 110int rese t 00000000000 54 trigger 111 wait for trigger from... send trigger to... x 55 ext trig x x ch3 ch2 ch1 ext trig x x ch3 ch2 ch1 mux set start address 100111000 ram address 55 mux set end address 100111001 ram address 56 mux select led 100111010 led select 56 mux clear 1001110100000000 56 mux next address 1001110110000000 56 mux previous address 1001110111000000 57 mux set rm 1001110100100000 57 mux reset rm 1001110101000000 57 mux fade 1001110100100 fade r3 fade r2 fade r1 57 mux set ptr 1 0 0 1 1 1 0 1 0 1 1 vector number 58 je (jump ==) 1 0 0 0 1 0 0 instructions skipped variable 1 variable 2 58 jge (jump >=) 1 0 0 0 1 0 1 instructions skipped variable 1 variable 2 59 jl (jump <) 1 0 0 0 1 1 0 instructions skipped variable 1 variable 2 59 jn e (jump <>) 1 0 0 0 1 1 1 instructions skipped variable 1 variable 2 60 ld (load) 1001 target variable 0 0 value 60 add number 1001 target variable 0 1 value 61 add variable 1001 target variable 1 1 0 0 0 0 variable 1 variable 2 61 sub number 1001 target variable 1 0 value 62 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 67 - 77 as3665 datasheet, confidential - sequencer commands table sequencer commands sub variable 1001 target variable 1 1 0 0 0 1 variable 1 variable 2 62 get adc 1 0 0 0 1 0 1 0 0 0 1 0 target variable 63 load sram 1 0 0 0 1 1 1 r/w sram address source/target variable 63 or 1000101 input variable 0 0 1 target variable 64 and 1000110 input variable 0 0 1 target variable 64 shift left 1000101 input variable 0 0 0 target variable 65 shift right 1000110 input variable 0 0 0 target variable 65 table 106. sequencer commands table command d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 see page ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 68 - 77 as3665 datasheet, confidential - registermap sequencer commands 11 registermap table 107. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 exec_enable 00h 00h ram_init chip_en p3_en p2_en p1_en exec_mode 01h 00h trig_input _on 0 p3_mode p2_mode p1_mode led_control1 02h 00h led8_on led7_on led6_on led5_on led4_on led3_on led2_on led1_on led_control2 03h 00h gpo_on fader_log lin3 fader_log lin2 fader_log lin1 temp_co mp_mod e led9_on gpo_control 04h 00h int_on_tri g sel_ext_ clock int_signa l int_mode gpo_sign al gpo_mode cp_control 05h 10h cp_down_hyst cp_on cp_auto_ on cp_mode_switching cp_mode cp_mode_switch 06h 37h cp_auto_ reset cp_skip_ on cp_max_ 5v4 led9_on _cp led8_on _cp led7_on _cp supervision 08h 81h auto_shu tdown osc_alwa ys_on ov_temp _status ov_temp _on adc_control 09h 00h adc_sing le_conve rsion adc_slow adc_cont inuous adc_select adc_msb_result 0ah 00h result_no t_ready adc<9:3> adc_lsb_result 0bh 00h adc<2:0> interrupt_status 0ch 40h ov_temp adc_eoc init_read y_int no_extcl ock_dete cted int3 int2 int1 interrupt_mask 0dh ffh ov_temp _masked adc_eoc _masked init_read y_int_ma sked no_extcl ock_dete cted_ma sked int3_mas ked int2_mas ked int1_mas ked temp_sense_ control 0eh 00h temp_me as_busy temp_se ns_on temp_int _ext variable_d 0fh 00h var_d led_current1 10h 00h led_current1 led_current2 11h 00h led_current2 led_current3 12h 00h led_current3 led_current4 13h 00h led_current4 led_current5 14h 00h led_current5 led_current6 15h 00h led_current6 led_current7 16h 00h led_current7 led_current8 17h 00h led_current8 led_current9 18h 00h led_current9 led_maxcurr1 19h 00h led4_max led3_max led2_max led1_max ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 69 - 77 as3665 datasheet, confidential - registermap sequencer commands led_maxcurr2 1ah 00h led8_max led7_max led6_max led5_max led_maxcurr3 1bh 00h led9_max audio_control 1ch 00h 0 0 audio_buf_gain audio_bu f_on audio_c mdset audio_on audio_agc 1dh 00h agc_time agc_ctrl led_temp 1fh 00h led_temp reset_control 3ch 00h force_res et chip_id1 3dh c9h 1 1 0 0 1 0 0 1 chip_id2 3eh 5xh 0 1 0 1 revision page_select 5fh 00h page_select cmd_0_msb 60h 00h cmd_0_msb cmd_0_lsb 61h 00h cmd_0_lsb cmd_1_msb 62h 00h cmd_1_msb cmd_1_lsb 63h 00h cmd_1_lsb cmd_2_msb 64h 00h cmd_2_msb cmd_2_lsb 65h 00h cmd_2_lsb cmd_3_msb 66h 00h cmd_3_msb cmd_3_lsb 67h 00h cmd_3_lsb cmd_4_msb 68h 00h cmd_4_msb cmd_4_lsb 69h 00h cmd_4_lsb cmd_5_msb 6ah 00h cmd_5_msb cmd_5_lsb 6bh 00h cmd_5_lsb cmd_6_msb 6ch 00h cmd_6_msb cmd_6_lsb 6dh 00h cmd_6_lsb cmd_7_msb 6eh 00h cmd_7_msb cmd_7_lsb 6fh 00h cmd_7_lsb cmd_8_msb 70h 00h cmd_8_msb cmd_8_lsb 71h 00h cmd_8_lsb cmd_9_msb 72h 00h cmd_9_msb cmd_9_lsb 73h 00h cmd_9_lsb cmd_a_msb 74h 00h cmd_a_msb cmd_a_lsb 75h 00h cmd_a_lsb cmd_b_msb 76h 00h cmd_b_msb cmd_b_lsb 77h 00h cmd_b_lsb cmd_c_msb 78h 00h cmd_c_msb table 107. register map (continued) register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 70 - 77 as3665 datasheet, confidential - registermap sequencer commands cmd_c_lsb 79h 00h cmd_c_lsb cmd_d_msb 7ah 00h cmd_d_msb cmd_d_lsb 7bh 00h cmd_d_lsb cmd_e_msb 7ch 00h cmd_e_msb cmd_e_lsb 7dh 00h cmd_e_lsb cmd_f_msb 7eh 00h cmd_f_msb cmd_f_lsb 7fh 00h cmd_f_lsb pwm_led1 80h 00h pwm_led1 pwm_led2 81h 00h pwm_led2 pwm_led3 82h 00h pwm_led3 pwm_led4 83h 00h pwm_led4 pwm_led5 84h 00h pwm_led5 pwm_led6 85h 00h pwm_led6 pwm_led7 86h 00h pwm_led7 pwm_led8 87h 00h pwm_led8 pwm_led9 88h 00h pwm_led9 pwm_gpo 8fh 00h pwm_gpo fader1 9bh 00h fader1 fader2 9ch 00h fader2 fader3 9dh 00h fader3 driver_setup1 a0h 20h fader_src1 loglin1 color_slope1 driver_setup2 a1h 20h fader_src2 loglin2 color_slope2 driver_setup3 a2h 20h fader_src3 loglin3 color_slope3 driver_setup4 a3h 20h fader_src4 loglin4 color_slope4 driver_setup5 a4h 20h fader_src5 loglin5 color_slope5 driver_setup6 a5h 20h fader_src6 loglin6 color_slope6 driver_setup7 a6h 20h fader_src7 loglin7 color_slope7 driver_setup8 a7h 20h fader_src8 loglin8 color_slope8 driver_setup9 a8h 20h fader_src9 loglin9 color_slope9 start_addr1 b0h 00h start_addr1 start_addr2 b1h 00h start_addr2 start_addr3 b2h 00h start_addr3 seq1_pc b4h 00h pc1 seq2_pc b5h 00h pc2 seq3_pc b6h 00h pc3 variable_a1 b8h 00h var_a1 table 107. register map (continued) register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 71 - 77 as3665 datasheet, confidential - registermap sequencer commands variable_a2 b9h 00h var_a2 variable_a3 bah 00h var_a3 variable_c bbh 00h var_c variable_b1 bch 00h var_b1 variable_b2 bdh 00h var_b2 variable_b3 beh 00h var_b3 sram0 d0h 00h sram_0 sram1 d1h 00h sram_1 sram2 d2h 00h sram_2 sram3 d3h 00h sram_3 sram4 d4h 00h sram_4 sram5 d5h 00h sram_5 sram6 d6h 00h sram_6 sram7 d7h 00h sram_7 sram8 d8h 00h sram_8 sram9 d9h 00h sram_9 sram10 dah 00h sram_10 sram11 dbh 00h sram_11 sram12 dch 00h sram_12 sram13 ddh 00h sram_13 sram14 deh 00h sram_14 sram15 dfh 00h sram_15 program_direct_a ccess feh 00h 96x16_bits_instruction_code see program direct access on page 43 register is r/w register is read-only table 108. information registers (only for demoboard software) register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 cp_mode_switch 06h 00h led9_hi gh_volt led9_lo w_volt see table 107 on page 68 led_low_voltage _status 07h 00h led8_lo w_volt led7_lo w_volt led6_lo w_volt led5_lo w_volt led4_lo w_volt led3_lo w_volt led2_lo w_volt led1_lo w_volt table 107. register map (continued) register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 72 - 77 as3665 datasheet, confidential - registermap sequencer commands temp_sense_ control 0eh 00h cp_skip_ status audio_agc 1dh 00h audio_di s_start audio_m an_start led_high_voltage _status 1eh 00h led8_lhi gh_volt led7_hi gh_volt led6_hi gh_volt led5_hi gh_volt led4_hi gh_volt led3_hi gh_volt led2_hi gh_volt led1_hi gh_volt mux1_lsb 20h 00h s1_led8 s1_led7 s1_led6 s1_led5 s1_led4 s1_led3 s1_led2 s1_led1 mux2_lsb 21h 00h s2_led8 s2_led7 s2_led6 s2_led5 s2_led4 s2_led3 s2_led2 s2_led1 mux3_lsb 22h 00h s3_led8 s3_led7 s3_led6 s3_led5 s3_led4 s3_led3 s3_led2 s3_led1 mux1_msb 24h 00h s1_gpo s1_led9 mux2_msb 25h 00h s2_gpo s2_led9 mux3_msb 26h 00h s3_gpo s3_led9 trigger_wait1 28h 00h ext_trigg er ch3_trigg er ch2_trigg er trigger_wait2 29h 00h ext_trigg er ch3_trigg er ch1_trigg er trigger_wait3 2ah 00h ext_trigg er ch2_trigg er ch1_trigg er audio_result 2fh 00h audio_result page_select 5fh 00h loop_cou nter_sele ct see table 107 on page 68 table1_startaddr c4h 00h table_start1 table2_startaddr c5h 00h table_start2 table3_startaddr c6h 00h table_start3 table1_endaddr c8h 00h table_end1 table2_endaddr c9h 00h table_end2 table3_endaddr cah 00h table_end3 table1_pointer cch 00h table_ptr1 table2_pointer cdh 00h table_ptr2 table3_pointer ceh 00h table_ptr3 register is r/w register is read-only table 108. information registers (only for demoboard software) (continued) register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 73 - 77 as3665 datasheet, confidential - application information external components 12 application information external components low esr input capacitors reduce input switching noise and reduce the peak current drawn from the battery. low esr output capacitors should be used to minimize vout ripple. ceramic capacitors are required and should be located as close to the device as is practical. x5r dielectric material is recommended due to their ability to maintain capacitance over wide voltage and temperature range. input, output and c 2v5 capacitor if a different input capacitor is chosen, ensure similar esr value and at least 0.6f capacitance at the maximum input supply voltage. larger capacitor values (c) for c bat may be used without limitations. flying capacitors if a different input capacitor is chosen, ensure similar es r value and at least 0.3f capacitance at the maximum out- put voltage. larger capacitor values (c) may be used without limitations. pcb layout guideline the high speed operation requires proper layout for optimum per formance. route the power traces first and try to min- imize the area and wire length of th e two high frequency/high current loops: 1. c bat to c fly1 and/or c fly2 2. c fly1 and/or c fly2 to c vcpout table 109. recommended input, output and c 2v5 capacitor name part number c tc code rated voltage size manufacturer c bat , c vcpout , c 2v5 grm188r60j105k 1.0f +/-15% x5r 6v3 0603 murata www.murata.com 223824613663 1.0f +/-10% x5r 10v 0603 phycomp www.phycomp.com table 110. recommended input, output and c 2v5 capacitor name part number c tc code rated voltage size manufacturer c fly1 , c fly2 grm155r60j474k 470nf +/-15% x5r 6v3 0402 murata www.murata.com c0603c474k4rac 470nf +/-10% x7r 16v 0603 kemet www.kemet.com ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 74 - 77 as3665 datasheet, confidential - application information led test the ground plane of the system should be connected to the layout of the as3665 only at a single point. this avoid noise to travel from the internal s witching node to the application - see figure 29 : figure 29. layout recommendation note: if component placement rules allow, move all components close to the as3665 it is possible to route the as3665 with only two planes to reduce the cost of the pcb. led test see led test on page 39 . !"# ! " !$ !%&' (( ) * +, - .!/ %( ! -&! 0!! + % ! ( '! -! '! 1 2 -&! 0!! ! +,2( ! '.!! ! !% "! 11 / %( ! ! !% +, ams ag technical content still valid www.austriamicrosystems.com revision 1.0.2 75 - 77 as3665 datasheet, confidential - package drawings and markings led test 13 package drawings and markings figure 30. wl-csp-25 (2.610x2.675mm) 0.5mm pitch marking note: line 1: austriamicrosystems logo line 2: as3665 line 3: encoded datecode (4 characters) figure 31. wl-csp-25 (2.610x2.675m m) 0.5mm pitch package dimensions the coplanarity of the balls is 40m. as3665 |
Price & Availability of AS3665-ZWLT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |